Friday evening, and the verification engineer is packing up at a normal hour for the first time in months. The regression suite that used to swallow five weeks of calendar time just finished in less than a day. Nobody hand-wrote a single new test. The engineer only supervised, watched the agent's reasoning, and stepped in twice.
That scene is not hypothetical. It is the working description of what Cadence and NVIDIA unveiled at Computex 2026: the industry's first fully autonomous virtual AI design engineer, an agent that pushes a chip from specification to verified RTL without step-by-step prompting. The system is the ChipStack AI Super Agent, now running at Level-5 autonomy, powered by NVIDIA Nemotron models and secured inside the NVIDIA OpenShell runtime.
The Five-Week Loop That Shrunk to One Day
Inside NVIDIA, this is not a demo. Thousands of engineers already burn billions of compute hours a year running millions of verification tests across the company's chip portfolio. With ChipStack agents in the loop, each engineer directs hundreds of dynamic simulations using Cadence Xcelium Logic Simulation and Jasper Formal Verification.
The headline number: over 40x faster RTL validation cycles, collapsing a typical five-week verification loop into less than a day. At leading-edge scale, that is the difference between shipping a GPU generation on time and missing the window entirely.
Rather than prompting the machine step by step, engineers now state intent. The agent evaluates intermediate results, decides what to do next, and iterates toward closure across:
- specification understanding and RTL generation
- verification planning and formal analysis
- simulation, debug, and design convergence
"We're taking the next step, moving from AI that assists engineers to autonomous virtual engineers that can implement real design and verification work," said Paul Cunningham, senior vice president and general manager of Cadence's System Verification Group. Teams can inspect, guide, and collaborate at any point, and the agent stays compatible with tools like Codex and Claude Code so the reasoning stays visible.
The Security Story Behind the Autonomy
Autonomy in chip design sounds risky, and for good reason. A design database is among the most valuable IP a company owns, and a rogue agent with broad tool access is a nightmare scenario. This is where NVIDIA OpenShell earns its place in the story.
OpenShell is a sandboxed runtime for autonomous agents that enforces governance at the infrastructure level. For ChipStack, that means:
- policy controls that decide what an agent may touch
- tool isolation so one agent's actions cannot bleed into another's
- managed access to design data, infrastructure, and compute
Sensitive IP stays inside the sandbox while the agent works, and every action is accountable. "By securing Cadence's ChipStack AI Super Agent with NVIDIA OpenShell and powering it with Nemotron models, Cadence is bringing governed autonomy to chip design workflows," said Timothy Costa, NVIDIA vice president and general manager of computational engineering.
The second differentiator is physics. Cadence couples the agent's behavior to its signoff-accurate design and verification engines, so AI decisions stay grounded in proven computational models rather than free-floating guesses. Trust, in other words, is engineered in, not bolted on.
The Bet That Started Nine Months Ago
Cadence acquired ChipStack in November 2025, shipped its first agentic product in February 2026, and at CadenceLIVE in April expanded into a family: ViraStack for custom and analog design, InnoStack for digital implementation and signoff, and AgentStack to orchestrate agentic workflows across the stack. The Level-5 ChipStack capabilities and the AgentStack framework reach early-access customers in the second half of 2026.
Cadence is not alone in the race. At the Design Automation Conference in late July, Synopsys demonstrated its Fully Autonomous Design Verification Workflow, built on its agentic platform and AgentEngineer technology and including NVIDIA's Nemotron 3 Ultra model, Agent Toolkit, and OpenShell runtime, claiming validated RTL up to 50x faster than other platforms. Two EDA giants, one runtime, the same destination.
NVIDIA is also eating its own cooking. It is deploying its Arm-based Vera CV100 CPU across its internal EDA workflows, with early tests showing 1.5x the performance of AMD Epyc Torrent systems on Synopsys VCS and Cadence Jasper, helping design Rosa, the 2028 CPU built on the Rigel core.
Underneath the benchmarks sits the quieter revolution: the job itself is changing. Verification engineers used to write tests and wait for results. Now they supervise outcomes, steer intent, and step in when the agent hesitates. The five-week loop becomes a lunch break, and the question shifts from whether chips get verified to who watches the watcher.
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